logic gate
英 [ˈlɒdʒɪk ɡeɪt]
美 [ˈlɑːdʒɪk ɡeɪt]
n. 逻辑门，逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)
牛津词典
noun
- 逻辑门，逻辑闸（以两种方式之一对所输入数据进行输出的电子开关）
an electronic switch that reacts in one of two ways to data that is put into it. A computer performs operations by passing data through a very large number of logic gates .
英英释义
noun
- a computer circuit with several inputs but only one output that can be activated by particular combinations of inputs
双语例句
- Within this context, the first chapter indicates quantum logic gate and the second chapter demonstrates composing and running of the quantum C-NOT gate.
本文第一章介绍了量子逻辑门，第二章介绍了量子C-NOT门的构成及运行，第三章和第四章是具体的研究工作。 - The special Flip-Flop, combination logic gate and improved topology of Prescaler, enable the Prescaler to intensify the low power-high speed tradeoff.
其中，采用了特殊的D触发器和组合逻辑门结构，改进了预置数分频器结构，能够使分频器工作在低功耗、高速度之间有比较好的折衷。 - Each particle in the system acts like the logic gate of a computer.
系统中每个粒子的作用类似电脑里的逻辑闸。 - Since any logic gate can be constructed by two-qubit controlled not gates ( CN gate) and one qubit rotation gate ( R gate), the realization of the CN and R gates has been studied extensively.
任意量子门都可以由二比特控制非门（CN门）和单比特旋转门（R门）组成。因此，人们致力于研究如何实现CN门和R门。 - Reversible logic gate cascade is an important part of reversible logic synthesis.
可逆逻辑门级联是可逆逻辑综合的重要组成部分。 - Diode transistor logic gate
二极管晶体管逻辑门 - On the basis of operation rules of fuzzy number and of logic gate operator the probabilities of occurrence of middle events and top events were calculated, thus provided basis on enhancing the reliability design of system.
根据模糊数及逻辑门算子的运算规则，计算出了各中间事件及顶事件发生的概率，为提高系统的可靠性设计提供了依据。 - Hermetically sealed, very high speed, logic gate optocoupler.
密封，非常高的速度，逻辑门光耦合器。 - This paper introduces a new concept of implication logic function and implication logic gate. The implication logic gate can be used as a basic unit in a large-scale digital IC to simplify circuitry and reduce power dissipation.
本文引出蕴函逻辑函数和蕴函逻辑门的新概念，利用蕴函逻辑门作为大规模数字集成电路的基本单元可以简化电路，减小电路的功耗。 - This paper introduces a new structure of numeral multilier: using one-level logic gate structure to realize array numeral multiplier, and using cmos technology to realize 8 × 8 ultraspeed array numeral multiplier with a new structure.
本文介绍了一种新的数码乘法器结构：采用一级逻辑门结构实现阵列式数码乘法器，并采用CMOS工艺技术实现新结构的8×8位超高速阵列式数码乘法器。